TMC2192 datasheet(29/69 Pages) CADEKA

29 / 69 page

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

relation to the PD port. Control register OMIX chooses

among the following set of coefﬁcients; either 0 1/8 1/2 7/8

1, 0 1/2 1 , or 0 1 to switch between the PD port and the over-

lay color. The timing diagram in Figure 22 identiﬁes the

three possible output formats that the mixer can produce.

Figure 21. Overlay Outputs

Hardware Keying

The KEY input switches the input to the Comp data path

between the composite video generated from the PD port and

the CVBS data bus on a pixel-by-pixel basis. This is a “soft”

switch is executed over 3 PCK periods to minimize out-of-

band transients. Keying is accomplished in the digital com-

posite video domain. The coefﬁcients for the mix are 0, 1/8,

1/2, 7/8, and 1 . The COMP output is the ﬁnal output for all

overlay functions.

Hardware keying is enabled by the key Control Register

HKEN. Normally, keying is only effective during the active

video portion of the encoded video line (as determined by

Control Register VA). That is, the horizontal blanking inter-

val is generated by the encoder even if the KEY signal is

held HIGH through horizontal blanking. However, it is pos-

sible to allow digital horizontal blanking to be passed

through from the CVBS bus to the COMP output by setting

key Control Register BUKEN HIGH. In this mode, KEY is

always active, and may be exercised at will.

The KEY input is registered into the encoder just as Pixel

data is clocked into the PD port. It is internally pipelined, so

the midpoint of the KEY transition occurs at the output of

the pixel that was input at the same time at the KEY signal.

Data Keying

Data keying for each channel Y, Cb, and Cr, is separately

enabled or disabled by the control registers DKEYDIS,

EKEYDIS, and FKEYDIS. On each channel the eight (8)

MSBs of the pixel data are compared against a maximum

key value and a minimum key value. If the pixel data is

greater than xKEYMIN and less than or equal to xKEY-

MAX, then a key match is signaled for that channel.

Figure 22. Data Keying

By allowing a window of possible key values on each chan-

nel the TMC2192 opens a key cube in the color space.

Parallel Microprocessor Interface

The parallel microprocessor interface is active when SER is

HIGH and employs a 12-line interface; an 8 bit data bus and

2 bit address location, 1 bit read/write select, and a chip

select controlling the timing. Two addresses are required for

device programming, one to the pointer and one to the data

location. When writing, the address is presented along with a

LOW on the R/W pin during the falling edge of CS. Eight

bits of data are presented on D7-0 during the subsequent ris-

ing edge of CS.

Table 19. Overlay Address Map

OL4-0

Result

Pixel data is passed through overlay mixer.

1-15

Overlay is mixed with PD or CVBS at the transitions.

Half amplitude PD or half amplitude CVBS is the output of COMP2.

17-31

Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions.

A>0

OL[4:0]

PDx

1/2C, 1/2OL

1/2G, 1/2OL

MixOUT (OMIX = 3)

7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL

1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL

MixOUT (OMIX = 2)

MixOUT (OMIX = 1)

65-6294-24

xKEYMAX

A<=B

KEY

MATCH

xKEYMIN

xCHANNEL

65-6294-25

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