AT90SCR100 datasheet(232/433 Pages) ATMEL

232 / 433 page

232

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 18-1.

USART Block Diagram

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only

used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, Parity Generator and Control logic for handling different serial frame formats. The

write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR0). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

18.4

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART0 supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA

UCSRB

UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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