EM351-RTR datasheet(99/240 Pages) ETC2

99 / 240 page

EM351 / EM357

actual overflow at the input to the receive FIFO. Two conditions will clear the error indication: setting the

appropriate SC_RXDMARST bit in the SC1_DMACTRL register, or loading the appropriate DMA buffer after it has

unloaded.

8.6.6

Interrupts

UART interrupts are generated on the following events:

Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_UARTTXIDLE)

Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_UARTTXFREE)

Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_UARTRXVAL)

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

Character received with parity error

Character received with frame error

Character received and lost when receive FIFO was full (receive overrun error)

To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable

the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

8-28

120-035X-000D

Preliminary

EM351-RTR 데이터시트(PDF) 99 Page - List of Unclassifed Manufacturers