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EM351-RTR 데이터시트(PDF) 77 Page - List of Unclassifed Manufacturers |
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EM351-RTR 데이터시트(HTML) 77 Page - List of Unclassifed Manufacturers |
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77 / 240 page ![]() EM351 / EM357 8-6 120-035X-000D Preliminary SCx_INTMODE SC1_INTMODE Serial Controller 1 Interrupt Mode Register Address: 0x4000A854 Reset: 0x0 SC2_INTMODE Serial Controller 2 Interrupt Mode Register Address: 0x4000A858 Reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 SC_TXIDLELEVEL SC_TXFREELEVEL SC_RXVALLEVEL Bitname Bitfield Access Description SC_TXIDLELEVEL [2] RW Transmitter idle interrupt mode - 0: edge triggered, 1: level triggered. SC_TXFREELEVEL [1] RW Transmit buffer free interrupt mode - 0: edge triggered, 1: level triggered. SC_RXVALLEVEL [0] RW Receive buffer has data interrupt mode - 0: edge triggered, 1: level triggered. 8.3 SPI - Master Mode The SPI master controller has the following features: Full duplex operation Programmable clock frequency (12 MHz max.) Programmable clock polarity and phase Selectable data shift direction (either LSB or MSB first) Receive and transmit FIFOs Receive and transmit DMA channels 8.3.1 GPIO Usage The SPI master controller uses the three signals: MOSI (Master Out, Slave In) – outputs serial data from the master MISO (Master In, Slave Out) – inputs serial data from a slave SCLK (Serial Clock) – outputs the serial clock used by MOSI and MISO |
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