EM351-RTR datasheet(82/240 Pages) ETC2

82 / 240 page

EM351 / EM357

SCx_SPICFG

SC1_SPICFG

SPI Configuration Register

Address: 0x4000C858 Reset: 0x0

SC2_SPICFG

SPI Configuration Register

Address: 0x4000C058 Reset: 0x0

SC_SPIRXDRV

SC_SPIMST

SC_SPIRPT

SC_SPIORD

SC_SPIPHA

SC_SPIPOL

Bitname

Bitfield

Access

Description

SC_SPIRXDRV

[5]

Receiver-driven mode selection bit (SPI master mode only). Clear this bit to initiate

transactions when transmit data is available. Set this bit to initiate transactions when the

receive buffer (FIFO or DMA) has space.

SC_SPIMST

[4]

Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave mode.

SC_SPIRPT

[3]

This bit controls behavior on a transmit buffer underrun condition in slave mode. Clear

this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to

this bit take effect when the transmit FIFO is empty and the transmit serializer is idle.

SC_SPIORD

[2]

This bit specifies the bit order in which SPI data is transmitted and received.

0: Most significant bit first.

1: Least significant bit first.

SC_SPIPHA

[1]

Clock phase configuration: clear this bit to sample on the leading (first edge) and set this

bit to sample on the second edge.

SC_SPIPOL

[0]

Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a

falling leading edge.

8-11

120-035X-000D

Preliminary

EM351-RTR 데이터시트(PDF) 82 Page - List of Unclassifed Manufacturers

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