EM351-RTR datasheet(93/240 Pages) ETC2

93 / 240 page

EM351 / EM357

8-22

120-035X-000D

Preliminary

Character transmitted (0 to 1 transition of SC_TWITXFIN)

Character received (0 to 1 transition of SC_TWIRXFIN)

Received and lost character while receive FIFO was full (receive overrun error)

Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable

the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

8.5.5

Registers

Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_RATELIN, and

SCx_RATEEXP registers.

SCx_TWISTAT

SC1_TWISTAT

TWI Status Register

Address: 0x4000C844 Reset: 0x0

SC2_TWISTAT

TWI Status Register

Address: 0x4000C044 Reset: 0x0

SC_TWICMDFIN

SC_TWIRXFIN

SC_TWITXFIN

SC_TWIRXNAK

Bitname

Bitfield

Access

Description

SC_TWICMDFIN

[3]

This bit is set when a START or STOP command completes. It clears on the next TWI bus

activity.

SC_TWIRXFIN

[2]

This bit is set when a byte is received. It clears on the next TWI bus activity.

SC_TWITXFIN

[1]

This bit is set when a byte is transmitted. It clears on the next TWI bus activity.

SC_TWIRXNAK

[0]

This bit is set when a NACK is received from the slave. It clears on the next TWI bus

activity.

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