EM351-RTR datasheet(104/240 Pages) ETC2

104 / 240 page

EM351 / EM357

active. This is useful for receiving messages that contain an initial byte count, since it allows software to set

the buffer end address at the last byte of the message.

As the DMA channel transfers data between the transmit or receive FIFO and a memory buffer, the DMA count

written or read. A transmit DMA channel has a single DMA count register (SCx_TXCNT) that applies to

whichever transmit buffer is active, but a receive DMA channel has two DMA count registers (SCx_RXCNTA/B),

one for each receive buffer. The DMA count register contents are preserved until the corresponding buffer, or

either buffer in the case of the transmit DMA count, is loaded, or until the DMA is reset.

The receive DMA count register may be written while the corresponding buffer is loaded. If the buffer is not

loaded, writing the DMA count register also loads the buffer while preserving the count value written. This

feature can simplify handling UART receive errors.

The DMA channel stops using a buffer and unloads it when the following is true:

(DMA buffer start address + DMA buffer count) > DMA buffer end address

Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is unloaded after

it is filled with data, but writing to the buffer end address or buffer count registers can also cause a buffer to

unload early.

Serial controller DMA channels include additional features specific to the SPI and UART operation and are

described in those sections.

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120-035X-000D

Preliminary

EM351-RTR 데이터시트(PDF) 104 Page - List of Unclassifed Manufacturers