910GL datasheet(108/426 Pages) INTEL

108 / 426 page

MCHBAR Registers

108

Datasheet

5.1.21

PMCFG—Power Management Configuration

MMIO Range:

MCHBAR

Address Offset:

F10h

Default Value:

00000000h

Access:

R/W

Size:

32 bits

Bit

Access &

Default

Description

31:5

Reserved

R/W

Enhanced Power Management Features Enable

0 = Legacy power management mode

1 = Reserved.

3:0

Reserved

5.1.22

PMSTS—Power Management Status

MMIO Range:

MCHBAR

Address Offset:

F14h

Default Value:

00000000h

Access:

R/W

Size:

32 bits

This register is Reset by PWROK only.

Bit

Access &

Default

Description

31:2

Reserved

R/WC/S

Channel B in self-refresh. This bit is set by power management hardware after

Channel B is placed in self refresh as a result of a Power State or a Reset Warn

sequence. It is cleared by power management hardware before starting Channel

B self refresh exit sequence initiated by a power management exit. It is cleared

by BIOS in a warm reset (Reset# asserted while pwrok is asserted) exit

sequence.

0 = Channel B not guaranteed to be in self-refresh.

1 = Channel B in Self-Refresh.

R/WC/S

Channel A in Self-refresh. Set by power management hardware after Channel

A is placed in self refresh as a result of a Power State or a Reset Warn

sequence. It is cleared by power management hardware before starting Channel

A self refresh exit sequence initiated by a power management exit. It is cleared

by the BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit

sequence.

0 = Channel A not guaranteed to be in self-refresh.

1 = Channel A in Self-Refresh.

910GL 데이터시트(PDF) 108 Page - Intel Corporation

910GL 데이터시트(HTML) 108 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL