910GL datasheet(111/426 Pages) INTEL

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EPBAR Registers—Egress Port Register Summary

Datasheet

111

6.1.2

EPLE1D—EP Link Entry 1 Description

MMIO Range:

EPBAR

Address Offset:

050h

Default Value:

0100h

Access:

R/WO, RO

Size:

32 bits

This register provides the First part of a Link Entry that declares an internal link to another Root

Complex Element.

Bit

Access

& Default

Description

31:24

01h

Target Port Number: This field specifies the port number associated with the

element targeted by this link entry (DMI). The target port number is with respect to

the component that contains this element as specified by the target component ID.

23:16

R/WO

00h

Target Component ID: This field identifies the physical or logical component that is

targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.

This value is a mirror of the value in the Component ID field of all elements in this

component. The value only needs to be written in one of the mirrored fields and it

will be reflected everywhere that it is mirrored.

15:2

Reserved

Link Type: This bit indicates that the link points to memory-mapped space (for

RCRB). The link address specifies the 64-bit base address of the target RCRB.

R/WO

Link Valid

0 = Link Entry is not valid and will be ignored.

1 = Link Entry specifies a valid link.

6.1.3

EPLE1A—EP Link Entry 1 Address

MMIO Range:

EPBAR

Address Offset:

058h

Default Value:

0000000000000000h

Access:

R/WO

Size:

64 bits

This register provides the second part of a Link Entry, which declares an internal link to another

Root Complex Element.

Bit

Access &

Default

Description

63:32

Reserved

31:12

R/WO

0 0000h

Link Address: This field provides the memory-mapped base address of the

RCRB that is the target element (DMI) for this link entry.

11:0

Reserved

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