910GL datasheet(112/426 Pages) INTEL

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EPBAR Registers—Egress Port Register Summary

112

Datasheet

6.1.4

EPLE2D—EP Link Entry 2 Description

MMIO Range:

EPBAR

Address Offset:

060h

Default Value:

02000002h

Access:

R/WO, RO

Size:

32 bits

This register provides the First part of a Link Entry that declares an internal link to another Root

Complex Element.

Bit

Access &

Default

Description

31:24

02h

Target Port Number: This field specifies the port number associated with the

element targeted by this link entry (PCI Express* x16 interface). The target port

number is with respect to the component that contains this element as specified

by the target component ID.

23:16

R/WO

00h

Target Component ID: This field identifies the physical or logical component that

is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.

This value is a mirror of the value in the Component ID field of all elements in this

component. The value only needs to be written in one of the mirrored fields and it

will be reflected everywhere that it is mirrored.

15:2

Reserved

Link Type:

1 = Link points to configuration space of the integrated device that controls the

x16 root port. The link address specifies the configuration address (segment,

bus, device, function) of the target root port.

R/WO

Link Valid

0 = Link Entry is not valid and will be ignored.

1 = Link Entry specifies a valid link.

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