SCL

SCS

SDO

t

4

t

5

t

2

t

3

t

7

t

6

t

1

SDI

t

8

A31

D0

D1

D15

D1

D0

A30

DON’T CARE

DON’T CARE

CDCUN1208LP

SCAS928 – MAY 2012

www.ti.com

Writing to the CDCUN1208LP

To initiate a SPI data transfer, the master (host) asserts the SCS (serial chip select) pin low (see Figure 32). The

first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCUN1208LP. This

bit signals if a read (first bit high) or a write (first bit low) will transpire. The master shifts data to the slave with

each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the

target register in the register file (see Figure 33). The 16 bits that follow are the data payload. If the master sends

an incomplete message, (i.e. the master de-asserts the SCS pin high prior to a complete message transmission),

then the slave aborts the transfer, and device makes no changes to the register file or the hardware. The master

signals the slave of the completed transfer and disables the SPI port by de-asserting the SCS pin high.

Reading from the CDCUN1208LP

As with the write operation, the master first initiates a SPI transfer by asserting the SCS pin low. The host signals

a read operation by shifting a logical high in the first bit position, signaling the slave that the master is initiating a

read data transfer from the slave. Thereafter, the master specifies the address of interest according to Figure 33.

During the 16 clock cycles that follow, the slave presents the data from the register specified in the first half of

the message on the SDO pin. The master signals the slave that the transfer is complete by de-asserting the SCS

pin high.

Block Write/Read Operation

The CDCUN1208LP supports a block write and block read operation. The master need only specify the lowest

address of the sequence of addresses that the host needs to access. The CDCUN1208LP will automatically

increment the internal register address pointer if the SCS pin remains active low after the SPI port finishes the

initial 32-bit transmission sequence. Each transmission of 16 bits (a data payload width) results in the slave

automatically incrementing the address pointer (provided the SCS pin remains active low for all sequences).

Figure 34. SPI Timing Diagram

Table 12. SPI Timing Specifications

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Clock Frequency for the SCL

20

MHz

SCS to SCL setup time

10

ns

SDI to SCL setup time

10

ns

SDO to SCL hold time

10

ns

SCL high duration

25

ns

SCL low duration

25

ns

SCL to SDO Setup time

10

ns

SCS Pulse Width

20

ns

SCL to SCS release time

10

ns

30

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