Microcontroller /

FPGA/DSP

MODE

PINS

I2C

SPI

NC

CDCUN1208LP

LVCMOS

LVCMOS

LVCMOS

OUT2N

3.3V

LVCMOS

LVCMOS

LVDS

LVDS

1.8V

LVDS

LVDS

LVDS

LVDS

3.3V

LVDS

LVDS

HCSL

HCSL

3.3V

Interface

&

Control

IN2P

/1,/2,/4,/8

IN1P

INSEL

VDD

Voltage

Regulator

GND

Power

Management

IN1N

IN2N

CDCUN1208LP

www.ti.com

SCAS928 – MAY 2012

DEVICE CONTROL USING THE HOST INTERFACE

Host configuration mode affords a greater degree of flexibility. Unlike pin configuration mode in which the pin

settings affect the entire device, host configuration mode enables the user to apply different settings to each

input and output port as depicted in Figure 30. This includes the ability to mix and match output type, edge rate

control, and output enable settings. The host interface is enabled/selected by strapping the MODE pin either high

interface as well. For instance, the user can configure the input divider (IDIV) to /8 in host configuration mode

only. Additionally, the system can power down the device through device registers.

OE and INSEL in Host Configuration Mode

In host configuration mode, the OE pin is no longer available; therefore buffers are controlled individually via the

host interface. The input multiplexer can be controlled either via the pin or via the device registers in accordance

with Table 11.

Figure 30. CDCUN1208LP Host Configuration – Typical Application

Copyright © 2012, Texas Instruments Incorporated

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