CDCUN1208LP datasheet(7/43 Pages) TI

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CDCUN1208LP

www.ti.com

SCAS928 – MAY 2012

CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVDS)

Unless otherwise noted, VDDOX = 1.8V, 2.5V, 3.3V; TA = –40°C to 85°C. See Figure 9, Figure 10, and Figure 11.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT

Output frequency

0.008

400

MHz

Output common mode voltage,

RL = 100 Ω

1.125

1.2

1.275

VDDOx = 2.5/3.3 V

VCM

Output common mode voltage,

RL = 100 Ω

0.9

VDDOx = 1.8 V

|VOD|

Differential output voltage

RL = 100 Ω, single-ended Pk-Pk

250

400

550

Change in magnitude of VOD for

ΔVOD

RL = 100 Ω

–50

complementary output states

Vring

Output overshoot and undershoot

Percentage of output amplitude VOD

20%

VOS

Output AC common mode

VIN, DIFF, PP = 0.9V, RL = 100 Ω, 2 pF

150

mVP-P

fout = 100 MHz, 10k-20M integration bandwidth,

200

RL = 100Ω

TADDJIT

Additive jitter(1)

fs, rms

fout = 400 MHz, 10k-20M integration bandwidth,

180

RL = 100Ω

ERC = Slow, 20% to 80%, ZL = 100Ω, 1pF,

800

VDDOx = 3.3V

ERC = Slow, 20% to 80%, ZL = 100Ω, 1pF,

700

VDDOx = 1.8V

tR/tF

Output rise/fall time

ERC = Medium., 20% to 80%, ZL = 100Ω, 1pF,

600

VDDOx = 3.3V

ERC = Medium., 20% to 80%, ZL = 100Ω, 1pF,

500

VDDOx = 1.8V

ERC = Fast, 20% to 80%, Z L = 100Ω, 1 pF

300

ODC

Output Duty Cycle

50/50 Input duty cycle

45%

55%

ISP

Output Short Circuit Current (single

Shorted to GND

-24

ended)

ISN

|IPN|

Output Short Circuit Current (differential)

Complementary outputs shorted together

ERC set to high rate. Input tr, tf > 0.6 V/ns, RL =

3.3

100

Ω, VDD = 2.5V, 3.3V

TDLYO

Propagation Delay

ERC set to high rate. Input tr, tf > 0.6 V/ns, RL =

3.8

100

Ω, VDD = 1.8V

ERC set to high rate. Input tr, tf > 0.6 V/ns, Equal

VDDOx,

tSKEW

Skew between outputs

RL = 100Ω

Pin mode. fout = 100 MHz, device in active mode

tOE

Output enable to stable clock output

µs

with outputs disabled, OE asserted

Host mode, fout = 100 MHz, device in power down

tPD

PD de-asserted to stable clock output

µs

mode, PD de-asserted

Time from power applied to stable clock

Pin mode, fout = 100 MHz, OE asserted, measured

tPU

output(2)

from time VDD is valid to stable output.

(1)

tRfin = tFfin > 0.6 V/ns.

(2)

Parameter depends significantly on power supply design and supply voltage rise time.

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