CDCUN1208LP datasheet(12/43 Pages) TI

12 / 43 page

CDCUN1208LP

SCAS928 – MAY 2012

www.ti.com

CLOCK OUTPUT BUFFER ELECTRICAL CHARACTERISTICS (OUTPUT MODE = LVCMOS)

(Continued)

Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see

Figure 15 and Figure 16.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.5V MODE

0.00

fout

Output frequency range

250

MHz

VDDOx = 2.375 V, IOH = -0.1 mA (All ERC Settings)

2.2

VDDOx = 2.375 V, IOH = -4 mA (ERC = SLOW)

1.7

LVCMOS High-level output

VOH

VDDOx = 2.375 V, IOH = - 6 mA (ERC = MED, FAST)

voltage

VDDOx = 2.375 V, IOH = -5 mA (ERC = SLOW)

1.6

VDDOx = 2.375 V, IOH = - 8 mA (ERC = MED, FAST)

VDDOx = 2.375 V, IOL = 0.1 mA (All ERC Settings)

0.1

VDDOx = 2.375 V, IOH = 4 mA (ERC = SLOW)

0.5

LVCMOS Low-level output

VOL

VDDOx = 2.375 V, IOH = 6 mA (ERC = MED, FAST)

voltage

VDDOx = 2.375 V, IOH = 5 mA (ERC = SLOW)

0.7

VDDOx = 2.375 V, IOL = 10 mA (ERC = MED, FAST)

VDDOx = 2.5 V, VO = 0.5 V; TA = 25°C

–45

LVCMOS High-level output

IOH

VDDOx = 2.5 V, VO = 0.9 V; TA = 25°C

–39

current

VDDOx = 2.5 V, VO = 1.25 V; TA = 25°C

–32

VDDOx = 2.5 V, VO = 2.0 V; TA = 25°C

LVCMOS Low-level output

IOL

VDDOx = 2.5 V, VO = 1.65 V; TA = 25°C

current

VDDOx = 2.5 V, VO = 1.25 V; TA = 25°C

tPLH, tPHL

Propagation delay

5.5

ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF

0.8

tSLEW-RATE

Output rise/fall slew rate

ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF

1.4

V/ns

ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF

tjitt-add

Additive jitter

fOUT = 100 MHz, 10k-20M integration bandwidth

280

tsk(o)

Output skew(1)

odc

Output Duty Cycle(2)(3)

fOUT = 100 MHz; Pdiv = 1

45%

55%

Output enable to stable clock

Pin mode. fout = 100 MHz, device in active mode with

tOE

µs

output

outputs disabled, OE asserted

PD de-asserted to stable clock

Host mode, fout = 100 MHz, device in power down mode,

tPD

µs

output

PD de-asserted

Time from power applied to

Pin mode, fout = 100 MHz, OE asserted, measured from

tPU

stable clock output(4)

time VDD is valid to stable output.

(1)

The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages..

(2)

Assumes 50% duty cycle at the input(s)

(3)

odc depends on output rise and fall time (tR/tF).

(4)

Parameter depends significantly on power supply design and supply voltage rise time.

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