A14

W

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SCS

SCL

SDO

A14

R

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

SDI

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

Hi-Z

Don’t Care

0

0

0

A3 A2 A1 A0

0

0

1

0

0

0

0

0

SPI Fixed Address

CDCUN1208LP Register Address

lsb

msb

A14

W

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D15 D14 D13 D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SCS

SCL

SDI

A14

R

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

SDI

D15 D14 D13 D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

Hi-Z

Don’t Care

CDCUN1208LP

www.ti.com

SCAS928 – MAY 2012

HOST INTERFACE HARDWARE INFORMATION

SPI Communication

A SPI communication link includes a master and one or more slaves. Table 9 lists the four signal lines that form

a SPI communication link. Figure 32 shows the format for SPI messages. The SPI master (host) initiates

communication by asserting SCS low. Information on SDI/SDO is latched on each rising edge of SCL. The first

bit transmitted on SDI establishes the direction of the SPI transfer. Next, the master transmits the address to be

written/read (up to 15 bits). If the operation is a write, the master transmits 16 data bits on SDI. If the transfer is a

read, the slave transmits 16 data bits on SDO (the master continues to clock the transfer via SCL). Figure 34 and

Table 12 show the timing specifications for SPI.

Figure 32. SPI Message Format

CDCUN1208LP SPI Addressing

Figure 33 shows how to construct the address field for SPI messages to/from the CDCUN1208LP. The device is

assigned a 4-bit fixed address (0001b). In order for the host to communicate with the CDCUN1208LP, the

address must include this fixed value in the correct position for the device to recognize the message.

Figure 33. CDCUN1208LP Device Addressing - SPI Mode

Copyright © 2012, Texas Instruments Incorporated

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