CDCUN1208LP

SCAS928 – MAY 2012

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Configuration of Output Type (OTTP)

Table 3 shows how to set the output buffer type using the OTTP pin. This setting affects all device outputs

equally. Certain combinations of output buffers include a dedicated power supply pin which must be properly

bypassed. If the device output configuration is set to LVCMOS, then the supply voltage applied establishes the

switching thresholds corresponding to the supply provided according to CLOCK OUTPUT BUFFER

ELECTRICAL CHARACTERISTICS (OUTPUT MODE = LVCMOS). For example, if OUT1 and OUT2 are

supplied with a 1.8V power supply via the VDDO1 pin, the switching thresholds are set to the 1.8V logic domain.

The system may have other logic supplies (1.8V, 2.5V, or 3.3V) connected to the device on different output

buffer supply domains simultaneously. This enables the device to clock devices operating on different supplies

without the need for external logic level translation buffers. The CDCUN1208LP automatically adjusts the

switching thresholds corresponding to these common logic power supply voltages. For more information

regarding the power supplies for the output section, see DEVICE POWER SUPPLY CONNECTIONS AND

SEQUENCING.

Table 3. CDCUN1208LP Pin Configuration of Output Type

OTTP (Pin 19)

OUTPUT TYPE

LOW

LVDS

HIGH

HCSL

OPEN

LVCMOS

Configuration of Edge Rate Control (ERC)

The CDCUN1208LP supports Edge Rate Control (ERC) used to tailor jitter and EMI performance from device

outputs. Table 4 shows the edge rate control setting. This setting affects all device outputs equally. Each edge

rate setting is unique to the output buffer type selected as described in CLOCK OUTPUT BUFFER

CHARACTERISTICS (OUTPUT MODE = LVDS), CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT

MODE = HCSL), and CLOCK OUTPUT BUFFER ELECTRICAL CHARACTERISTICS (OUTPUT MODE =

LVCMOS).

Table 4. CDCUN1208LP Pin Configuration of Output Edge Rate

ERC (Pin 31)

OUTPUT EDGE RATE

LOW

SLOW

HIGH

MEDIUM

OPEN

FAST

Control of Output Enable (OE)

Table 5 shows how the output enable pin controls the device outputs. The OE pin is sampled continuously so

that the application may turn on/off the output buffers at any time.

Table 5. CDCUN1208LP Pin Control of Output Enable

OE (Pin 32)

OUTPUT ENABLE

LOW

DISABLED

HIGH

ENABLED

OPEN

(1)

Leaving the Output Enable pin OPEN will cause the CDCUN1208LP to malfunction. This pin must be

driven high or low at all times

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