PRI _REF

SEC _REF

Internal

Reference Clock

Primary Clock

Secondary Clock

Primary Clock

CDCUN1208LP

SCAS928 – MAY 2012

www.ti.com

SMART INPUT MULTIPLEXER (INMUX)

The Smart Multiplexer supports manual and automatic switching between IN1 and IN2. If enabled, the Smart

Multiplexer switches automatically between clock inputs based on a prioritization scheme shown in Table 8. If

using the Smart Multiplexer Auto Mode, the frequencies of the clocks applied to the smart multiplexer via IN1 and

IN2 (via the divider) may differ by up to 20%. The phase relationship between clock inputs has no restriction. The

Upon the detection of a loss of signal on the input with higher priority, the smart multiplexer switches over to the

other clock input on the first incoming rising edge. During this switching operation, the output of the smart

multiplexer is low. Upon restoration of the higher priority clock, the smart multiplexer waits until it detects four

complete cycles from the higher priority clock prior to switching the output of the smart multiplexer back to the

higher priority clock. During this switching operation, the output of the smart multiplexer remains high until the

next falling edge as shown in Figure 29.

Pin Configuration of the Smart Input Multiplexer (INMUX)

Table 8 shows how to control the Smart Input Multiplexer. In Pin Configuration mode, the INSEL pin is sampled

continuously so that the application may select the input clock at any time.

Table 8. Control of INMUX via the INSEL Pin

INSEL(Pin 2)

IN1 BUFFER SETTING

IN2 BUFFER SETTING

LOW

ON and selected by INSEL Multiplexer

OFF

HIGH

OFF

ON and selected by INSEL Mux

OPEN

Smart Multiplexer selects input. IN1 is the primary input (it has the highest priority, therefore if it is available,

the smart multiplexer selects IN1)

Figure 29. CDCUN1208LP Smart Multiplexer Operation

(1)

This implementation does not implement a phase build-out mechanism; rather, analog filtering insuring a smooth transition at device

outputs.

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