| 전자부품 데이터시트 검색엔진 |
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AN2014 데이터시트(PDF) 20 Page - STMicroelectronics |
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AN2014 데이터시트(HTML) 20 Page - STMicroelectronics |
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20 / 65 page ![]() Recommendations to improve EEPROM reliability AN2014 20/65 DocID10701 Rev 10 Figure 12. Latchup mechanism and protection 1. Protection is only recommended if latchup risk is identified. 3.2.3 ST EEPROM latchup protection During the qualification process, samples from three different lots are tested for voltage overshoots (positive and negative injections). Figure 13 shows the levels of stress applied to the tested devices. Figure 13. Latchup test conditions 1. The device does not latch up within the gray areas. 3.3 Power supply considerations The power supply also has a major impact on the operating reliability of the EEPROM device. Ai11084b SCR is switched on by an external stress coming from an I/O pin. 5V VCC VSS Latch up risk minimized RP<50Ω RP<1KΩ SRC 5V VSS VCC I/O EEPROM I or V stress SRC I/O High current(often destructive) Fail ai10858 Fail Current Injection 100mA 100mA Good = Class A Good = Class A 0.5 x V CCmax 1.5 x VCCmax Overvoltage |
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