AN2014 datasheet(45/65 Pages) STMICROELECTRONICS

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AN2014

Software considerations

5.5

Cycling endurance and data retention

Even if EEPROM devices are able to withstand a very high number of write cycles, the

EEPROM should not be used in replacement for a non-volatile RAM buffer. The cycling

budget during application life has to be considered.

5.5.1

Cycling and data retention qualification procedures

Cycling qualification

During the cycling qualification, ST EEPROM devices are cycled with a dedicated test

program which allows to program in one single write cycle the whole memory array with the

same byte value. ST can thus guarantee that, for each write operation performed with this

test program:

•

each memory array cell is cycled once;

•

the logic and the associated internal voltages that control the write cycles are cycled

once.

Therefore, in a device specified as 4 Mcycles, the qualification results allow to consider that

each byte can be cycled 4 million times.

Data retention qualification

The data retention qualification tests check that the data written to the EEPROM remain

available with a correct programming level after a bake at 150 °C during 1000 hours (high

temperature significantly accelerates the data retention drift).

5.5.2

Optimal cycling with ECC

Some ST EEPROM devices embed an internal ECC (error correction code) logic which

improves data retention performance. This ECC logic must be taken into account when

defining the application cycling budget.

For devices embedding the ECCx4, the ECCx4 logic compares each group of 4 bytes with 6

additional EEPROM ECC bits associated with each group of 4 bytes. As a result, if a single

bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects

it and corrects it with the correct value in the output stream of data (read data). The

EEPROM cell read reliability is therefore improved by using this feature.

However even if a single byte has to be written, 4 bytes are internally modified (plus the

ECC bits), that is, the addressed byte is cycled together with the three other bytes making

up the group.

For example:

•

Writing one byte at address 0000h internally programs this byte plus the 3 following

bytes and ECC bits.

•

Writing the next byte at address 0001h internally programs this byte plus the 3

contiguous bytes (address 0000h, 0002h, 0003h), and the ECC bits.

•

Writing the next byte at address 0002h internally programs this byte plus the 3

contiguous bytes (address 0000h, 0001h, 0003h), and the ECC bits.

•

Wring the next byte at address 0003h, internally programs this byte plus the 3

contiguous bytes (address 0000h, 0001h, 0002h), and the ECC bits.

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