AN2014 datasheet(46/65 Pages) STMICROELECTRONICS

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Software considerations

AN2014

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DocID10701 Rev 10

This example shows that each byte was cycled 4 times, although each byte was written only

once. We can therefore conclude that writing data by groups of 4 bytes benefit of the highest

number of write cycles.

Note:

A group of 4 bytes is composed of bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3],

where N is an integer.

Refer to AN2440 “Consequences of the embedded ECC on the EEPROM behavior” for

more details concerning the ECC.

For devices embedding the ECCx1, the ECC logic compares each byte with 4 additional

EEPROM ECC bits associated with each byte. As a result, if a single bit in a byte of data

happens to be erroneous during a read operation, the ECC detects it and corrects it with the

correct value in the stream of read data. The EEPROM cell read reliability is therefore

improved by using this feature.

5.5.3

Cycling and temperature dependence

Write cycling and retention endurance are independent of the value of VCC but directly

depend on the operating temperature. The higher the temperature, the lower the cycling

performance. Refer also to Section 1.1.3: Cycling limit of EEPROM cells.

EEPROM cycling safe operating area

For a robust application design, the safe cycling operating areas shown in Figure 39 have to

be considered as a safe maximum cycling value for each byte of the memory, going above

this safe operating area is not recommended.

Figure 39. Write cycling versus temperature

0.01

0.1

-40

255075

100

125

150

Temperature (oC)

Cell cycling safe operating area

1Kbit to 1Mbit devices

4 million cycles specification (devices identified with process letters K or T)

1 million cycles specification (devices older than process letter K)

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