LAN9730 datasheet(54/222 Pages) MICROCHIP

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LAN9730/LAN9730i

DS00001946A-page 54

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4.4.2.2

TX Data Format

The TX data section begins at the third DWORD in the TX buffer (after TX Command A and TX Command B). The loca-

tion of the first byte of valid buffer data to be transmitted is specified in the Data Start Offset field of TX Command A.

Table 4-43, "TX Data Start Offset" shows the correlation between the setting of the LSBs in the Data Start Offset field

and the byte location of the first valid data byte.

TX data is contiguous until the end of the buffer. The buffer may end on a byte boundary. Unused bytes at the end of

the packet will not be sent to the TLI for transmission.

4.4.2.3

TX Buffer Fragmentation Rules

Transmit buffers must adhere to the following rules:

• Each buffer may start and end on any arbitrary byte alignment.

• The first buffer of any transmit packet can be any length.

• Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in

length.

• The final buffer of any transmit packet can be any length.

TABLE 4-42:

TX COMMAND B FORMAT

Bits

Description

31:15

RESERVED

TX Checksum Enable (CK)

If this bit is set in conjunction with the first segment bit (FS) in TX Command A and the TX Checksum

Offload Engine Enable bit (TXCOE_EN) in the Checksum Offload Engine Control register (COE_CR),

the TX checksum offload engine (TXCOE) will calculate an L3 checksum for the associated frame.

Note:

This bit only needs to be set for the first buffer of a frame.

Add CRC Disable

When set, the automatic addition of the CRC is disabled.

Disable Ethernet Frame Padding

When set, this bit prevents the automatic addition of padding to an Ethernet frame of less than 64

bytes. The CRC field is also added despite the state of the Add CRC Disable field.

RESERVED

10:0

Frame Length (bytes)

This field indicates the total number of bytes in the current frame. This length does not include the off-

set or padding. If the Frame Length field does not match the actual number of bytes in the frame, the

Transmitter Error (TXE) flag will be set (in the Interrupt Status Register (INT_STS) and the interrupt

Endpoint). This value is read by the TX FIFO controller, and is used to determine the amount of data

that must be moved from the TX data FIFO into the TLI block. If the byte count is not aligned to a

DWORD boundary, the TX FIFO Controller will issue the correct byte enables to the TLI layer during

the last write. Invalid bytes in the last DWORD will not be passed to the TLI for transmission.

TABLE 4-43:

TX DATA START OFFSET

Data Start Offset[1:0]

First TX Data Byte

D[31:24]

D[23:16]

D[15:8]

D[7:0]

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