LAN9730 datasheet(17/222 Pages) MICROCHIP

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 2012-2015 Microchip Technology Inc.

DS00001946A-page 17

LAN9730/LAN9730i

1Transmit Data

(Internal PHY

Mode)

TXD0

IS/O8

(PD)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 125 for additional information.

Transmit Data

(External

PHY Mode)

TXD0

(PD)

In External PHY Mode, this pin functions as the

transmit data 0 output to the external PHY.

General Pur-

pose I/O 4

(Internal PHY

Mode Only)

GPIO4

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

EEPROM

Disable Con-

figuration

Strap

EEP_DISABLE

(PD)

This strap disables the autoloading of the

EEPROM contents. The assertion of this strap

does not prevent register access to the EEPROM.

0 = EEPROM is recognized if present.

1 = EEPROM is not recognized even if it is pres-

ent.

See Note 2-1 for more information on configura-

tion straps.

TABLE 2-1:

MII INTERFACE PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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