LAN9730 datasheet(14/222 Pages) MICROCHIP

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LAN9730/LAN9730i

DS00001946A-page 14

 2012-2015 Microchip Technology Inc.

Management

Data

(Internal PHY

Mode)

MDIO

IS/O8

(PU)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 125 for additional information.

Management

Data

(External

PHY Mode)

MDIO

IS/O8

(PD)

In External PHY Mode, this pin provides the man-

agement data to/from the external PHY.

General Pur-

pose I/O 1

(Internal PHY

Mode Only)

GPIO1

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

Note:

This pin may serve as the

PME_MODE_SEL input when Internal

PHY and PME Modes of operation are

in effect. Refer to Chapter 5.0, "PME

Operation" for additional information.

Management

Clock

(Internal PHY

Mode)

MDC

IS/O8

(PU)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 125 for additional information.

Management

Clock

(External

PHY Mode)

MDC

(PD)

In External PHY Mode, this pin outputs the man-

agement clock to the external PHY.

General Pur-

pose I/O 2

(Internal PHY

Mode Only)

GPIO2

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

TABLE 2-1:

MII INTERFACE PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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