LAN9730 datasheet(101/222 Pages) MICROCHIP

101 / 222 page

 2012-2015 Microchip Technology Inc.

DS00001946A-page 101

LAN9730/LAN9730i

4.8.4

ENABLE DESCRIPTOR RAM AND FLAG ATTRIBUTE REGISTERS AS SOURCE

The EEPROM Emulation Enable (EEM) bit of the Hardware Configuration Register (HW_CFG) must be configured by

the software device driver to use the Descriptor RAM and the Attributes registers for custom operation. Upon assertion

of EEPROM Emulation Enable (EEM), the hardware will utilize the descriptor information contained in the Descriptor

RAM, the Attributes registers, and the values of the items listed in Section 4.8.1 to facilitate custom operation.

4.8.5

INHIBIT RESET OF SELECT SCSR ELEMENTS

The software device driver must take care to ensure that the contents of the Descriptor RAM and SCSR register content

critical to custom operation using Descriptor RAM are preserved across reset operations other than POR. The driver

must configure the Reset Protection (RST_PROTECT) bit of the Hardware Configuration Register (HW_CFG) in order

to accomplish this.

The following registers have contents that can be preserved across all resets other than POR. Consult the register’s

description for additional details.

• Descriptor RAM

• Attributes registers

• MAC Address High Register (ADDRH) and MAC Address Low Register (ADDRL)

• Hardware Configuration Register (HW_CFG)

• LED General Purpose IO Configuration Register (LED_GPIO_CFG)

• General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE)

4.9

Device Clocking

The device requires a fixed-frequency 25 MHz clock source. This is typically provided by attaching a 25 MHz crystal to

the XI and XO pins. The clock can optionally be provided by driving the XI input pin with a single-ended 25 MHz clock

source. If a single-ended source is selected, the clock input must run continuously for normal device operation.

Internally, the device generates its required clocks with a phase-locked loop (PLL). It reduces its power consumption in

several of its operating states by disabling its internal PLL and derivative clocks. The 25 MHz clock remains operational

in all states where power is applied.

4.10

Device Power Sources

The device may be soft powered by the USB bus or self powered via external power supplies. The following external

3.3 V power supplies are required when power is not being furnished by the USB bus:

• VDD33IO, VDD33A

The device includes an internal 1.2 V regulator which provides power to the internal core logic. This regulator may be

optionally disabled if an external 1.2 V power source is available. The internal core regulator is controlled via the

CORE_REG_EN pin. When disabled, +1.2 V must be supplied to the device by an external source. Refer to Chapter

3.0 for information on proper power connections when enabling or disabling the internal core regulator.

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