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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 79 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 79 Page - Zilog, Inc. |
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79 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access be independently programmed as 2, 3, or 4 clock cycles long (more if Wait cycles are used), thereby increasing or decreasing the speed at which all DMA signals change. Second, the four signals in each port (I/O Request, Memory Request, Read, and Write) can each have its active trailing edge terminated one-half clock cycle early. This adds a further flexibility by allowing functions such as shorter-than-normal Read or Write signals to go inactive before data starts to change. Figure 24 illustrates the general capability, which is described laterin “Timing”on page151” Figure 24. Variable Cycle Length Events and Actions Table 10 gives an overview of the events that can cause specific actions by the DMA, depending on how it is programmed. The events are conditions in the DMA’s internal registers, signals from the I/O device, or instructions on thedatabus forwhich theDMA watches. CLK T1 T2 T3 T4 2-Cycle 3-Cycle 4-Cycle Early Ending for Control Signals |
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