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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 59 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 59 Page - Zilog, Inc. |
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59 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Bus Control Most DMACs do not control the system bus in the same way that a CPU controls it. For example, many DMACs do not have a straightforward interface to the system data bus but rather multiplex a portion of the memory address onto the data bus, from which it must be latched by external logic. Nor do most DMACs generate all of the bus control signals that the CPU generates, and therefore they lack some degree of bus control when they operate. The Z80 DMA is unique among 8-bit DMACs because it generates exactly the same bus control signals for read and write cycles that the Z80 CPU does, and also because it has exactly the same logical and electrical interface to the data and address buses as the CPU. This means the other system components cannot discern the difference between the Z80 DMA and CPU; control by these devices is totally interchangeable. In the sequential DMA transfer method (a read cycle followed by a write cycle), it also means that the Z80 DMA pins can be tied directly to the corre- sponding Z80 CPU pins without any of the external interfacing logic that some DMACs require. This property considerably simplifies design and lowers part counts. Programmability How a DMAC starts, transfers data, and stops is determined by control information written to the DMAC by the CPU prior to the transfer. Status registers, which can be read by the CPU to determine the transfer condition after the DMAC stops transferring, are also typically provided. The degree of programmability is directly related to the DMACs flexibility in handling a variety of transfer tasks. Most DMACs are limited in their programmability. The Z80 DMA, by contrast, has over 140 bits of control information used to tailor the device (and retailor it between operations) for a wide variety of tasks and environments. |
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