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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 44 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 44 Page - Zilog, Inc. |
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44 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels Figure 10. CTC Read Cycle CTC Counting and Timing Figure 11 illustrates the timing diagram for the CTC Counting and Timing modes. In the Counter mode, the edge (rising edge is active in this example) from the external hardware connected to pin CLK/TRG, decrements the down- counter in synchronization with the System Clock Φ. This CLK/TRG pulse must have a minimum width and the minimum period must not be less than twice the System clock period. Although there is no setup time requirement between the active edge of the CLK/TRG and the rising edge of Φ,if the CLK/TRG edge occurs closer than a specified minimum time, the decrement of the down-counter will be delayed one cycle of Φ. Immediately after the 1 to 0 decrement of the down-counter, the ZC/TO output is pulsed true. In the Timer mode, a pulse trigger (user selectable as either active High or active Low) at the CLK/TRG pin enables the timing function on the second succeeding rising edge of Φ. As in the Counter mode, the triggering pulse is CS0. CS1, CE IORQ RD M1 DATA Channel Address T1 T1 T2 TWA T3 CLK OUT |
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