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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 98 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 98 Page - Zilog, Inc. |
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98 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Interrupts Conditions and Methods The Z80 CPU prioritizes external events in the following order: 1. Bus Requests (BUSREQ) 2. Non-Maskable Interrupts (NMI) 3. Maskable Interrupts (INT) In addition to bus requests, the DMA normally allows only maskable inter- rupts (INT) and uses them in CPU Mode 2, which allows interrupt vectors. Non-maskable interrupts are typically reserved for extreme priority events such as power-failure signaling. The DMA can be programmed to interrupt the CPU under the following conditions: • After the DMA’s RDY line has gone active and before the DMA requests the bus (interrupt on RDY). • On an end-of-block, when the contents of the byte counter match the contents of the block-length register. • On a byte match, when the contents of the match-byte register (after masking by the mask-byte register) corresponds to a data byte being transferred or searched. The DMA cannot have control of the bus when it interrupts the CPU. Signalingonthe INT line while the DMA is bus master generates periodic pulses to an external device. These pulses are not perceived by the Z80 CPU. Therefore, at stop-on-end-of-block or byte match, the DMA first releases the bus before interrupting the CPU, as shown in Figure 32. If the DMA is programmed to interrupt on end-of-block and also to Auto Restart on end-of-block, an interrupt occurs (and should be acknowledged for continued operation) at each end-of-block. However, the end-of-block |
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