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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 62 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 62 Page - Zilog, Inc. |
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62 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access • Programmable Force Ready Condition • Programmable Active State for Ready Line • Programmable DMA Enable • Complete System Bus Mastering • No External Logic Needed for Sequential Transfers in Z80 Environments Overview The Z80 DMA performs data transfers and searches in a wide variety of 8-bit CPU environments. This DMA is unique among DMACs because it takes full control of the system address, data, and control buses, and is therefore a special-purpose processor when enabled by the CPU to function in this unique way. The DMA also provides complete interfacing to the system bus. For example, in a Z80 CPU environment, the Z80 DMA generates the same signal levels and timings, including tristate control, which the Z80 CPU generates to accomplish a transfer. It normally does this without external TTL packages, which other DMAs may require. For this reason, and because of its extensive programmability for operating on data and dataflow, the Z80 DMA can be called a special-purpose transfer processor. It unburdens not only the CPU but also the system designer. The Z80 DMA is also unique in other respects. First, it generates two port addresses instead of one. Because both addresses can be either variable or fixed, the memory-to-memory or I/O-to-I/O transfers can be done with a single channel, whereas other DMACs may require more than one channel or may not do such transfers at all. The capability of the Z80 DMA’s channel surpasses the capability of any other available monolithic DMAC channel to service either fast or slow devices. In addition to having a Wait line for extending cycles, the basic |
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