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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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Z80 데이터시트(PDF) 34 Page - Zilog, Inc. |
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Z80 데이터시트(HTML) 34 Page - Zilog, Inc. |
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34 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels CTC OPERATING MODES Overview At power-on, the Z80 CTC state is undefined. Asserting RESET puts the CTC in a known state. Before a channel can begin counting or timing, a channel control word and a time constant data word must be written to the appropriate registers of that channel. Additionally, if a channel has been programmed to enable interrupts, an interrupt vector word must be written to the CTC’s interrupt control logic. (For further details, refer the “CTC Programming” on page 18) When the CPU has written all of these words to the CTC, all active channels are programmed for immediate operation in either the COUNTER mode or the TIMER mode. CTC COUNTER Mode In CTC COUNTER mode, the CTC counts edges of the CLK/TRG input. This mode is programmed for a channel when its Channel Control Word is written with bit 6 set. The channel’s external clock (CLK/TRG) input is monitored for a series of triggering edges. After each, in synchronization with the next rising edge of Φ (the System clock), the down-counter (which is initialized with the Time Constant Data word at the start of each sequence of down-counting) is decremented. Although there is no setup time requirement between the triggering edge of the External clock and the rising edge of Φ (Clock), the down-counter is not decremented until the following pulse. A channel’s External clock input is pre programmed by bit 4 of the channel control word to trigger the decrementing sequence with either a high- or a low-going edge. In Channels 0, 1, or 2, when the down-counter is successively decremented from the original time constant (until it reaches zero), the Zero Count (ZC/ TO) output pin for that channel is pulsed active (High). Due to package pin limitations, this pin does not exist on Channel 3 and so this pin may only be |
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