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GXM 데이터시트(PDF) 120 Page - National Semiconductor (TI) |
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GXM 데이터시트(HTML) 120 Page - National Semiconductor (TI) |
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120 / 244 page ![]() www.national.com 120 Revision 3.1 Integrated Functions (Continued) 4.4 GRAPHICS PIPELINE The graphics pipeline of the GXm processor includes a BitBLT/vector engine which has been optimized for Microsoft Windows. The hardware supports pattern gen- eration, source expansion, pattern/source transparency, and 256 ternary raster operations. The block diagram of the graphics pipeline is shown in Figure 4-11. 4.4.1 BitBLT/Vector Engine BLTs are initiated by writing to the GP_BLT_MODE regis- ter, which specifies the type of source data (none, frame buffer, or BLT buffer), the type of the destination data (none, frame buffer, or BLT buffer), and a source expan- sion flag. Figure 4-11. Graphics Pipeline Block Diagram Pattern Hardware Raster Operation Output Aligner BE PAT SRC DST BE Internal Bus Interface Unit Graphics Scratchpad RAM BitBLT Buffers and Memory X-Bus C-Bus Pipeline BE = Byte Enable PAT = Pattern Data SRC = Source Data DST = Destination Data Output Aligner Source Expansion Control Logic DRAM Interface Register Access Controller Key: |
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