CS89712 datasheet(68/170 Pages) CIRRUS

68 / 170 page

CS89712

DS502PP2

3. REGISTER SET

The 89712 contains multiple register ranges.

An 8 kbyte segment of memory in the range

0x8000.0000 to 0x8000.3FFF is for registers that

control non-Ethernet functions. Section 3.1 gives

an overview of these while Sections 3.3 through

3.16 provide register bit details.

Ethernet port registers are accessed through two

separate ranges: a 16 byte window of eight registers

and a 4 Kbyte page of registers. Section 3.2 ex-

plains Ethernet Port register access, and Sections

3.17 to 3.20 give bit details.

3.1 Non-Ethernet Registers

Table 31 shows the internal non-Ethernet registers

of the CS89712 when the CPU is configured to a

little endian memory system. Table 32 shows the

differences that occur when the CPU is configured

to a big endian memory system for byte-wide ac-

cess to Ports A, B, and D. All the internal registers

are inherently little endian (i.e., the least significant

byte is attached to bits 7 to 0 of the data bus).

Hence, the system Endianness affects the addresses

required for byte accesses to the internal registers,

resulting in a reversal of the byte address required

to read/write a particular byte within a register.

There is no effect on the register addresses for word

accesses. Bits A[1:0] of the internal address bus are

only decoded for Ports A, B, and D (to allow

read/write to individual ports). For all other regis-

ters, bits A[1:0] are not decoded, so that byte reads

will return the whole register contents onto the

CS89712’s internal bus, from where the appropri-

ate byte (according to the endianness) will be read.

To avoid the additional complexity, it is preferable

to perform all internal register accesses as word op-

erations, except for ports A to D which are explic-

itly designed to operate with byte accesses, as well

as with word accesses.

Writes to bits that are not explicitly defined in the

internal area are legal and will have no effect.

Reads from bits not explicitly defined in the inter-

nal area are legal but will read undefined values.

All the internal addresses should only be accessed

as 32-bit words and are always on a word bound-

ary, except for the PIO port registers, which can be

accessed as bytes. Address bits in the range A[0:5]

are not decoded (except for Ports A–D), this means

each internal register is valid for 64 bytes (i.e., the

SYSFLG1

appears

locations

0x8000.0140 to 0x8000.017C). There are some

gaps in the register map but registers located next

to a gap are still only decoded for 64 bytes.

The GPIO port registers are byte-wide and can be

accessed as a word but not as a half-word. These

registers additionally decode A[1:0].

Note: All byte-wide registers should be accessed as

words (except Port A to Port D registers, which are

designed to work in both word and byte modes).

All register bit alignment starts from the LSB of the

The registers which interact with the 32 kHz clock or

which could change during readback (i.e., RTC data

registers, SYSFLG1 register (lower 6-bits only), the

TC1D and TC2D data registers, port registers, and

interrupt status registers), should be read twice and

compared to ensure that a stable value has been read.

All internal registers are reset to zero by a system

reset (i.e., nPOR, nURESET, or nPWRFL signals

becoming active), except for the DRAM refresh pe-

riod register (DPFPR), the Real-Time Clock data

MR), which are only reset by nPOR becoming ac-

tive. This ensures that the DRAM contents and

system time are preserved through a user reset or

power fail condition.

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