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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS89712 데이터시트(PDF) 77 Page - Cirrus Logic |
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CS89712 데이터시트(HTML) 77 Page - Cirrus Logic |
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77 / 170 page  CS89712 DS502PP2 77 3.3 Ethernet Port 4 Kbyte Memory Register Map The following Table shows the CS89712 Ethernet Port internal register map: Internal Offset # of Bytes Type Description Cross Reference Bus Interface Registers 0000h 4 Reserved 0004h 28 - Reserved Note 2 0022h 2 RW Master Interrupt Enable Section 3., “REGISTER SET”, Section 3.17, “Ethernet Bus Interface Reg- isters” 0038h 8 - Reserved Note 2 0040h 2 RW EEPROM Command Section 2.24, “Programming the EEPROM”, Section 3.17, “Ethernet Bus Interface Reg- isters” 0042h 2 RW EEPROM Data Section 2.24, “Programming the EEPROM”, Section 3.17, “Ethernet Bus Interface Reg- isters” 0044h 12 - Reserved Note 2 0050h 2 RD Received Frame Byte Counter Section 3.17, “Ethernet Bus Interface Reg- isters”, Section 2.32, “Basic Receive Operation” 0052h 174 - Reserved Note 2 Status and Control Registers 0102 2 RW Receive Configuration Section 3.2.3, “Ethernet Status/Control Registers” 0104 2 RW Receive Control see above 0106 2 RW Transmit Configuration see above 0108 2 RW Transmit Command see above 010A 2 RW Buffer Configuration see above 0112 2 RW Line Control see above 0114 2 RW Self Control see above 0116 2 RW Bus Control see above 0118 2 RW Test Control see above 0120 2 RD Interrupt Status Queue 0124 2 RD Receive Event 0124 2 RD alternate Receive Event 0128 2 RD Transmit Event 012C 2 RD Buffer Event 0130 2 RD Receive Miss 0132 2 RD Transmit Collision 0134 2 RD Line Status 0136 2 RD Self Status Table 36. Ethernet Port 4 Kbyte Memory Register Address Map |
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