CS89712 datasheet(92/170 Pages) CIRRUS

92 / 170 page

CS89712

DS502PP2

3.6.5

INTSR3 Interrupt Status Register 3 (address 0x8000.2240)

This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the CS89712.

Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Table 44.

3.6.6

INTMR3 Interrupt Mask Register 3 (address 0x8000.2280)

This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new features of the

CS89712. Please refer to INTSR3 for individual bit details.

3.7 Expansion Memory Configuration Registers

3.7.1

MEMCFG1 Memory Configuration Register 1 (address 0x8000.0180)

Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (nCS[6]) is used inter-

nally for the on-chip SRAM, and the configuration is hardwired for 32-bit-wide, minimum- wait-state operation.

nCS[7] is used for the on-chip Boot ROM and the configuration field is hardwired for 8-bit-wide, minimum-wait-state

operation. Data written to the configuration fields for either nCS[6] or nCS7 will be ignored. Two of the chip selects

(nCS[4:5]) can be used to access two CL-PS6700 PC CARD controller devices, and when either of these interfaces

is enabled, the configuration field for the appropriate chip select in the MEMCFG2 register is ignored. When the PC

CARD1 or 2 control bit in the SYSCON2 register is disabled, then nCS[4] and nCS[5] are active as normal and can

be programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the six external chip

selects are active for 256 Mbytes and the timing and bus transfer width can be programmed individually. This is ac-

complished by programming the six-byte-wide fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2.

All bits in these registers are cleared by a system reset (except for the nCS[6] and nCS[7] configurations).

The Memory Configuration Register 1 is a 32-bit read / write register which sets the configuration of the four expan-

sion and ROM selects nCS[0:3]. Each select is configured with a 1-byte field starting with expansion select 0.

7:1

Reserved

DAIPINT

Bit

Description

DAIINT: DAI interface interrupt. The cause must be determined by reading the DAI status regis-

ter. It is mapped to the FIQ interrupt on the ARM720T processor

Table 44. INTSR3

7:1

Reserved

DAIINT

31:24

23:16

15:8

7:0

nCS[3] configuration

nCS[2] configuration

nCS[1] configuration

nCS[0] configuration

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