CS89712 datasheet(30/170 Pages) CIRRUS

30 / 170 page

CS89712

DS502PP2

2.16 Internal UARTs and SIR Encoder

The CS89712 contains two built-in UARTs that of-

fers similar functionality to National Semiconduc-

tor’s 16C550A device. Both UARTs can support

bit rates of up to 115.2 kbits/s and include two 16-

byte FIFOs: one for receive and one for transmit.

One of the UARTs (UART1) supports the three

modem control input signals CTS, DSR, and DCD.

The additional RI input, and RTS and DTR output

modem control lines are not explicitly supported

but can be implemented using GPIO ports in the

CS89712. UART2 has only the RX and TX pins.

UART operation and line speeds are controlled by

the UBLCR1 (UART bit rate and line control).

Three interrupts can be generated by UART1: RX,

TX, and modem status interrupts. Only two can be

generated by UART2: RX and TX. The RX inter-

rupt is asserted when the RX FIFO becomes half

full or if the FIFO is non-empty for longer than

three character length times with no more charac-

ters being received. The TX interrupt is asserted if

the TX FIFO buffer reaches half empty. The mo-

dem status interrupt for UART1 is generated if any

of the modem status bits change state. Framing and

parity errors are detected as each byte is received

and pushed onto the RX FIFO. An overrun error

generates an RX interrupt immediately. All error

bits can be read from the 11-bit wide data register.

The FIFOs can also be programmed to be one byte

depth only (i.e., like a conventional 16450 UART

with double buffering).

The CS89712 also contains an IrDA (Infrared Data

Association) SIR protocol encoder as a post-pro-

cessing stage on the output of UART1. This encod-

er can be optionally switched into the TX and RX

signals of UART1, so that these can be used to

drive an infrared interface directly. If the SIR pro-

tocol encoder is enabled, the UART TXD1 line is

held in the passive state and transitions of the

RXD1 line will have no effect. The IrDA output pin

Address

(W/B)

Contents

Byte Lanes to Memory / Ports / Registers

Big Endian Memory

Little Endian Memory

7:0

15:8

23:16

31:24

7:0

15:8

23:16

31:24

Word + 0 (W)

11223344

Word + 1 (W)

11223344

Word + 2 (W)

11223344

Word + 3 (W)

11223344

Word + 0 (H)

11223344

Word + 1 (H)

11223344

Word + 2 (H)

11223344

Word + 3 (H)

11223344

Word + 0 (B)

11223344

Word + 1 (B)

11223344

Word + 2 (B)

11223344

Word + 3 (B)

11223344

Note: Bold indicates active byte lane.

Table 20. Effect of Endianness on Write Operations

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