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CS89712 데이터시트(PDF) 94 Page - Cirrus Logic

부품명 CS89712
상세설명  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 데이터시트(HTML) 94 Page - Cirrus Logic

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CS89712
94
DS502PP2
Value
No. of Wait States
Random
No. of Wait States
Sequential
00
4
3
01
3
2
10
2
1
11
1
0
Table 46. Values of the Wait State Field at 18 MHz
Bit 3
Bit 2
Bit 1
Bit 0
Wait States
Random
Wait States
Sequential
0
000
8
3
0
001
7
3
0
010
6
3
0
011
5
3
0
100
4
2
0
101
3
2
0
110
2
2
0
111
1
2
1
000
8
1
1
001
7
1
1
010
6
1
1
011
5
1
1
100
4
0
1
101
3
0
1
110
2
0
1
111
1
0
Table 47. Values of the Wait State Field at 36 MHz
Bit
Description
6
SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a
quad word boundary to take advantage of faster access times from devices that support page
mode. The sequential access will be faulted after four words (to allow video refresh cycles to
occur), even if the access is part of a longer sequential access. In addition, when this bit is not
set, non-sequential accesses will have a single idle cycle inserted at least every four cycles so
that the chip select is de-asserted periodically between accesses for easier debug.
7
CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during
accesses to the selected expansion device. This will provide a timing reference for devices that
need to extend bus cycles using the EXPRDY input. Back-to-back (but not necessarily page
mode) accesses will result in a continuous clock.
Table 48. MEMCFG



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