CS89712 datasheet(35/170 Pages) CIRRUS

35 / 170 page

CS89712

DS502PP2

frame synchronization. Each transition of LRCK

delineates the left and right halves of an audio sam-

ple. When LRCK transitions from high-to-low the

next 16 bits make up the right side of a sample.

When LRCK transitions from low-to-high the next

16 bits make up the left side of a sample.

2.17.2.3

DAI Signals

MCLK is used as an input to the CS89712 for gen-

erating the DAI timing. This signal is also usually

used as an input to a DAC/ADC as an oversampled

clock. This signal is fixed at 256 times the audio

sample frequency.

The SCLKbit clock is used as the bit clock input

into the DAC/ADC. This signal is fixed at 128 or

64 times the audio sample frequency.

LRCK is used as a frame synchronization input to

the DAC/ADC. This signal is fixed at the audio

sample frequency. This signal is clocked out on the

negative going edge of SCLK.

SDOUT is used for sending playback data to a

DAC. This signal is clocked out on the negative go-

ing edge of the SCLK output.

SDIN is used for receiving record data from an

ADC. This signal is latched by the CS89712 on the

positive going edge of SCLK.

Figure 7. Digital Audio Clock Generation

PLL

(73.728MHz)

EXTCLK

(11.2896)

MUX

(AUDCLKSRC)

Programmable Divide

(AUDIV)

128(fs)

/32

Audio Bit Clock 128/64(fs) SCLK

LRCLK(Fs)

MCLK

7-bit

counter

fixed at 4

Audio

Sample

Frequency

(fs)

Audio

Data

FIFO

Control

256Fs

BUZZ

BUZZ-PIN

DAI

MSB

LRCK

SCLK

Left Channel

Right Channel

SDATA

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

SDATA

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

SDATAI

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

128 SCLKs

MSB

LSB

Figure 8. CS89712 - Digital Audio Interface Timing – MSB / Left Justified format

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