CS89712 datasheet(17/170 Pages) CIRRUS

17 / 170 page

CS89712

DS502PP2

2.7.2

Dynamic Clock Switching

The clock frequency used for the CPU and the bus-

es is controlled by programming the CLKCTL[1:0]

bits in the SYSCON3 register. When this register is

written, clock switching logic waits until the clock

that is currently in use and the newly programmed

clock source are both low, and then switches from

the previous clock frequency to the new clock with-

out a glitch on the clocks.

2.7.3

Ethernet Port Clock Oscillator

A 20 MHz quartz crystal or CMOS clock input is

required by the Ethernet port. If a CMOS clock in-

put is used, it should be connected the to XTAL1

pin, with the XTAL2 pin left open. The clock sig-

nal should be 20 MHz

±0.01% with a duty cycle

between 40% and 60%. The specifications for the

crystal are described in Section 5.3.

2.8 Interrupt Controller

When unexpected events arise during the execution

of a program (i.e., interrupt or memory fault) an ex-

ception is usually generated. When these excep-

tions occur at the same time, a fixed priority system

determines the order in which they are handled.

Table 6 shows the priority order of the exceptions.

The CS89712 interrupt controller has two interrupt

types: interrupt request (IRQ) and fast interrupt re-

quest (FIQ). The interrupt controller has the ability

to control interrupts from 22 different FIQ and IRQ

sources. Of these, seventeen are mapped to the IRQ

input and five sources are mapped to the FIQ input.

FIQs have a higher priority than IRQs. If two inter-

rupts are received from within the same group (IRQ

or FIQ), the order in which they are serviced must

be resolved in software. All interrupts are level sen-

sitive; that is, they must conform to the following

sequence:

1) The interrupting device (either external or in-

ternal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask

EXPCLK

(internal)

RUN

Interrupt /

WAKEUP

CLKEN

Figure 4. CLKEN Timing Exiting the Standby State

t42

Note: t42=0.125 sec. to 0.25 sec.

Priority

Exception

Highest

Reset

Data Abort

.FIQ

.IRQ

Prefetch Abort

Lowest

Undefined Instruction,

Software Interrupt

Table 6. Exception Priority Handling

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