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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC87373 데이터시트(PDF) 24 Page - National Semiconductor (TI) |
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PC87373 데이터시트(HTML) 24 Page - National Semiconductor (TI) |
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24 / 174 page  1.0 Signal/Pin Connection and Description (Continued) 24 www.national.com Revision 1.1 1.4.13 Configuration Straps and Testing 3V_DDCSCL 113 I/O SWSM VSB3 3.3V Level DDC Serial Clock. SMBus serial clock signal with 3.3V logic levels for Data Display Channel interface. External pull-up resistor to VDD3 is required. 5V_DDCSCL 114 I/O SWSM VSB3 5V Level DDC Serial Clock. SMBus serial clock signal with 5V logic levels for VGA monitor interface. External pull-up resistor to VDD5 is required. 3V_DDCSDA 115 I/O SWSM VSB3 3.3V Level DDC Serial Data. SMBus serial data signal with 3.3V logic levels for Data Display Channel interface. External pull-up resistor to VDD3 is required. 5V_DDCSDA 116 I/O SWSM VSB3 5V Level DDC Serial Data. SMBus serial data signal with 5V logic levels for VGA monitor interface. External pull-up resistor to VDD5 is required. SMB1_SCL 87 I/O SWSM VSB3 Bus 1 Serial Clock. Serial clock signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SCL 88 I/O SWSM VSB3 Bus 2 Serial Clock. Serial clock signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB1_SDA 89 I/O SWSM VSB3 Bus 1 Serial Data. Serial data signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SDA 90 I/O SWSM VSB3 Bus 2 Serial Data. Serial data signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. Signal Pin(s) I/O Buffer Type Power Well Description BADDR 30 I INTS VDD3 Base Address. Sampled at VDD Power-Up reset to determine the base address of the configuration Index-Data register pair, as follows: – No pull-down resistor (default) - 2Eh-2Fh –10K Ω1 external pull-down resistor - 4Eh-4Fh The external pull-down resistor must be connected to VSS. TRIS 26 I INTS VDD3 TRI-STATE Device. Sampled at VDD Power-Up reset to force the device to float all its output and I/O pins. No pull-down resistor (default) - normal pin operation –10K Ω1 external pull-down resistor - floating device pins – The external pull-down resistor must be connected to VSS. When TRIS is set to 0 (by an external pull-down resistor), TEST must be 1 (left unconnected). TEST 27 I INTS VDD3 XOR Tree Test Mode. Sampled at VDD Power-Up reset to force the device pins into a XOR tree configuration. – No pull-down resistor (default) - normal device operation –10K Ω1 external pull-down resistor - pins configured as XOR tree. The external pull-down resistor must be connected to VSS. When TEST is set to 0 (by an external pull-down resistor), TRIS must be 1 (left unconnected). Signal Pin(s) I/O Buffer Type Power Well Description |
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