PC87373 datasheet(74/174 Pages) NSC

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5.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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Revision 1.1

The functionality of the GPIO port is divided into:

• Basic functionality: Includes configuration of, writing to and reading from the GPIO pins (described in Section 5.2)

• Enhanced functionality: Includes wake-up event detection and system notification (described in Section 5.3)

In addition, the GPIO port can be operated in one of the following modes:

• Separate Data I/O: Separate registers are available for Data In (GPDI) and for Data Out (GPDO) in addition to the Data

In/Out register (GPDIO) and to the enhanced functionality registers (GPEVST and GPEVEN).

• Common Data I/O: Only the Data In/Out register (GPDIO) is available.

5.2 BASIC FUNCTIONALITY

The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and

GPDI (or GPDIO). The configuration and operation of a single pin GPIOXn (pin ‘n’ in port ‘X’) is shown in Figure 10.

Figure 10. GPIO Basic Functionality

5.2.1

Configuration Options

The GPCFG1 register controls the following basic configuration options, as shown in Figure 10:

• Port Direction: Controlled by Output Enable (bit 0).

• Output Type: Push-pull vs. open-drain; it is controlled by Output Buffer Type (bit 1) by enabling/disabling the upper tran-

sistor of the output buffer.

• Static Pull-Up: May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2).

• Pin Lock: GPIO pin may be locked to prevent any changes in the output value and/or the output configuration. The lock

is controlled by bit 3. It disables writes to GPDO and GPDIO registers bits, to bits 3

−0 of GPCFG1 register (including the

Lock bit itself) and to bit 4 of GPCFG2 register.

Data Out

Data In

Output

Enable

Output

Lock

Type

Static

Pull-Up

Enable

Push-Pull =1

Pull-Up

Control

Read Only

Read/Write

(Bit 3)

(Bit 2)

(Bit 1)

(Bit 0)

Lock

GPIO Pin Conﬁguration Registers 1 and 2

(GPCFG1)

LPC Bus

VDD-Powered

Load

(Bit 4)

Lock

No_Vdd

(GPCFG2)

(GPDI)

(GPDO)

Lock

PC87373 데이터시트(PDF) 74 Page - National Semiconductor (TI)

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