PC87373 datasheet(41/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.1

3.3.2

TRI-STATing Module Output

The pins of the Legacy modules (Serial Ports, Parallel Port, Floppy Disk Controller, Keyboard and Mouse Controller, MIDI

Port, Game Port) and FSCM module can be ﬂoated (TRI-STATEd). When the TRI-STATE Control bit (bit 0) is set in the

specific module configuration register (at index F0h of the specific Logical Device in the configuration space) and the module

is disabled (see Section 3.3.1), the module output signals are floated (TRI-STATEd) and the I/O signals are configured as

inputs (note that the logic level at the inputs is ignored by the module, which is disabled).

Figure 7 shows the control mechanism for TRI-STATing the pins of a Legacy module.

Figure 7. Control of TRI-STATing Legacy Module Pins

3.4 INTERNAL ADDRESS DECODING

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded in the functional block to determine the offset of the accessed register

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address

register are forced to 0 (read only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2, and KBC are limited to the I/O address range of 00h to 7FXh only

(bits 15-11 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses

the MIDI Port, Game Port and all of the non-legacy logical devices, including the FSCM, SWC and GPIO, are configurable

within the full 16-bit address range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel

Port). The KBC has two I/O base addresses with some implied dependency between them. For more details, see the de-

scription of the base address register for each logical device.

Fast

Disable

xxxDIS1

SIOCF6

TRI-

STATE

Control

Conﬁguration

Global

Enable

GLOBEN

SIOCF1

Activation

Bit (bit 0)

Index 30h

Device Conﬁguration

Legacy Module

Module

Enable

Module

(Index F0h)

Legacy

Enable

Output

Buffer

1. Wherever the bit is implemented

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