PC87373 datasheet(87/174 Pages) NSC

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6.0 System Wake-Up Control (SWC) (Continued)

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Revision 1.1

Special LED Control

The Special LED control is the default LED control option when a Lithium backup battery is connected to VBAT pin (VBAT >

VBATLOW). Two regular LEDs must be connected to the GRN_LED and the YLW_LED pins, according to configuration “b”

(Active High) in Figure 16.

In this option, LED operation is controlled by the bits of XLEDCTL register (at offset 02h; see Section 6.3.5 on page 92) and

by the SLP_S3, SLP_S5 and PWRGD_PS pins. When the system is in sleep state S5 (SLP_S5 = 0), both LEDs are off.

When the system is in sleep state S3 (SLP_S3 = 0) or S1 (SLP_S1 bit is set), the green LED blinks and the yellow LED is

off. The green and yellow LED operation is reversed when the system is in the working state (S0) and the Main power supply

is not functional (PWRGD_PS = 0). When the system is in working state (S0) and the Main power supply is within the spec-

ified limits, SW_CTL bit selects the active LED (On) of the two, and the other LED is turned off.

The blinking rate of the LEDs is 1 Hz with a duty cycle of 50%.

Table 36 on page 92 shows the states of the GRN_LED and YLW_LED pins. The LEDs are connected according to config-

uration “b” (see Figure 16 on page 85); therefore, a LED is On when the pin is TRI-STATEd; it is Off when the pin is at low

level (0).

6.2.6

Special Power Management Functions

Last Power State

Last Power State function saves the system power state when an AC power failure occurs.

When either the VDD3 or VSB3 power supply falls below the minimum limit, the SWC samples the value of the SLP_S3 signal.

If SLP_S3 is sampled low, this indicates an orderly shutdown of the Main supply through the S3-S5 sleep states; however,

if SLP_S3 is sampled high, this indicates a Power Fail condition, caused either by turning off the mechanical switch (G2

state) or by an AC power failure. The sampled value is powered by the VBAT backup supply, which preserves its value

throughout the Power Fail condition when both VDD3 and VSB3 supplies are off (see Section 2.1.2 on page 27) and until AC

power returns. When the system exits Power Fail (i.e., when VSB3 power is back on), this read-only bit serves as a snapshot

of the system state before the power was turned off.

The level of the SLP_S3 signal is sampled in LAST_PWR_STATE read-only bit in SWC_CTL register (see Section 6.3.3 on

page 90).

In case of a power failure, both VDD and VSB power supplies fall simultaneously. Therefore, the power failure is detected

either by VDD3 falling below VDD3OFF, or by VSB3 falling below VSB3OFF, whichever occurs ﬁrst.

The LAST_PWR_STATE bit is reset to 0 at VBAT Power-Up (see Section 2.2.1 on page 30).

Backup Battery Status

This function detects the status of the backup battery (VBAT). When the battery voltage is below the specification (VBAT <

VBATLOW), GOOD_BAT and LAST_PWR_STATE bits in SWC_CTL register (see Section 6.3.3 on page 90) are reset. In this

case, the value of LAST_PWR_STATE bit is incorrect and must be ignored.

If the battery voltage is within specified limits (VBAT >VBATLOW), GOOD_BAT bit is set when either the VDD3 or the VSB3

power supply falls below the minimum limit.

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