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PC87373 데이터시트(PDF) 14 Page - National Semiconductor (TI) |
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PC87373 데이터시트(HTML) 14 Page - National Semiconductor (TI) |
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14 / 174 page ![]() 1.0 Signal/Pin Connection and Description (Continued) 14 www.national.com Revision 1.1 1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY The signal DC characteristics of the pins described in Section 1.4 on page 16 are denoted by buffer type symbols, which are defined in Table 1 and described in further detail in Section 13.2 on page 153. The pin multiplexing information refers to two different types of multiplexing: q Multiplexed, denoted by a slash (/) between pins in the diagrams in Section 1.1. Pins are shared between two differ- ent functions. Each function is associated with different board connectivity. Normally, the function selection is deter- mined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS on power-up in order to comply with the board implementation. q Multiple Mode, denoted by an underscore (_) between pins in the diagrams in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection may be controlled by the device driver through the registers of the functional block and do not require a special BIOS setup on power-up. These pins are not considered multiplexed pins from the PC87373 configuration perspective. The mode selection method (registers and bits), as well as the signal specification in each mode, are described within the functional description of the relevant functional block. Table 1. Buffer Types Symbol Description INGP Input, Game Port compatible, with Schmitt Trigger INT Input, TTL compatible INTS Input, TTL compatible, with Schmitt Trigger INTS4 Input, TTL compatible, with 400 mV Schmitt Trigger INPCI Input, PCI 3.3V compatible INULR Input, power, resistor protected (not characterized) AI Input, analog (0-5.5V tolerant) Op/n Output, TTL/CMOS compatible, push-pull buffer capable of sourcing p mA and sinking n mA ODn Output, TTL/CMOS compatible, open-drain buffer capable of sinking n mA OPCI Output, PCI 3.3V compatible, AO Output, analog (0-5.5V tolerant) SWSM Input/Output switch, SMBus compatible PWR Power pin GND Ground pin |
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