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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC87373 데이터시트(PDF) 153 Page - National Semiconductor (TI) |
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PC87373 데이터시트(HTML) 153 Page - National Semiconductor (TI) |
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153 / 174 page  13.0 Device Characteristics (Continued) 153 www.national.com Revision 1.1 13.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 14. The charac- teristics describe the general I/O buffer types defined in Table 1 on page 14. For exceptions, refer to Section 13.2.12 on page 156. The DC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. 13.2.1 Input, Game Port Compatible with Schmitt Trigger Symbol: INGP 13.2.2 Input, TTL Compatible Symbol: INT 13.2.3 Input, TTL Compatible, with Schmitt Trigger Symbol: INTS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.75 VSUP 1 1. VSUP is VDD, VSB or VPP according to the input power well. 5.52 2. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.52 0.3 VSUP 1 V VHY Input Hysteresis 3003 3. Not tested. Guaranteed by characterization. mV IIL Input Leakage Current 0 < VIN <VSUP ±14 4. Maximum 20 µA for all pins together. Not tested. Guaranteed by characterization. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V IIL 2 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0<VIN <VSUP 3 3. VSUP is VDD3 or VSB3 according to the input power well. ±14 4. Maximum 20 µA for all pins together (for exceptions, refer to Section 13.2.12 on page 156). Not tested. Guaran- teed by characterization. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 2502 2. Not tested. Guaranteed by characterization. mV IIL 3 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0<VIN <VSUP 4 4. VSUP is VDD3 or VSB3 according to the input power well. ±15 5. Maximum 20 µA for all pins together (for exceptions, refer to Section 13.2.12 on page 156.). Not tested. Guaran- teed by characterization. µA |
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