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LAN9250 데이터시트(PDF) 211 Page - Microchip Technology

부품명 LAN9250
상세설명  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 데이터시트(HTML) 211 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001913A-page 211
LAN9250
A block diagram of the main components of the PHY can be seen in Figure 12-1.
12.2.2
100BASE-TX TRANSMIT
The 100BASE-TX transmit data path is shown in Figure 12-2. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
12.2.2.1
100BASE-TX Transmit Data Across the Internal MII Interface
For a transmission, the Host MAC drives the transmit data onto the internal MII TXD bus and asserts the internal MII
TXEN to indicate valid data. The data is in the form of 4-bit wide 25 MHz data.
FIGURE 12-1:
PHY BLOCK DIAGRAM
FIGURE 12-2:
100BASE-TX TRANSMIT DATA PATH
HP Auto-MDIX
TXPA/TXNA
RXPA/RXNA
To External
Ethernet Pins
10/100
Transmitter
10/100
Reciever
MII
MAC
Interface
MII
MDIO
Auto-
Negotiation
To Host MAC
To Host MAC
PLL
PHY Management
Control
Registers
From
System Clocks Controller
Interrupts
To System
Interrupt Controller
Port x
MAC
100M
TX Driver
MLT-3
Converter
NRZI
Converter
4B/5B
Encoder
Magnetics
CAT-5
RJ45
100M
PLL
Internal
MII 25 MHz by 4 bits
Internal
MII Transmit Clock
25MHz by
5 bits
NRZI
MLT-3
MLT-3
MLT-3
MLT-3
Scrambler
and PISO
125 Mbps Serial
MII MAC
Interface
25MHz
by 4 bits



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