LAN9250 datasheet(198/421 Pages) MICROCHIP

198 / 421 page

LAN9250

DS00001913A-page 198

 2015 Microchip Technology Inc.

11.15.3

HOST MAC ADDRESS LOW REGISTER (HMAC_ADDRL)

This read/write register contains the lower 32-bits of the physical address of the Host MAC. The contents of this register

are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is

detected. The least significant byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most

significant byte of this register is loaded from address 04h of the EEPROM. Section 11.9, "Host MAC Address," on

page 156 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of

the Ethernet physical address. Please refer to Section 13.4, "EEPROM Loader," on page 290 for more information on

the EEPROM Loader.

This register used to specify the address used for Perfect DA, Magic Packet and Wakeup frames, the unicast destination

address for received pause frames, and the source address for transmitted pause frames. This register is not used for

packet filtering.

Offset:

03h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Physical Address [31:0]

This field contains the lower 32-bits (31:0) of the Physical Address of the

Host MAC. The content of this field is undefined until loaded from the

EEPROM at power-on. The host can update the contents of this field after the

initialization process has completed.

R/W

FFFFFFFFh

LAN9250 데이터시트(PDF) 198 Page - Microchip Technology