ST72325AR7-Auto datasheet(173/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

I2C bus interface (I2C)

Doc ID 13770 Rev 3

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16.7.5

I2C data register (DR)

16.7.6

I2C own address register (OAR1)

6:0

CC[6:0]

7-bit clock divider

These bits select the speed of the bus (fSCL) depending on the I

2C mode. They are

not cleared when the interface is disabled (PE = 0).

Refer to Section 19: Electrical characteristics for the table of values.

Note: The programmed fSCL assumes no load on SCL and SDA lines.

Table 87.

CCR register description (continued)

Bit

Name

Function

Reset value: 0000 0000 (00h)

543

D[7:0]

Table 88.

DR register description

Bit

Name

Function

7:0

D[7:0]

8-bit Data Register

These bits contain the byte to be received or transmitted on the bus.

Transmitter mode: Byte transmission start automatically when the software writes

in the DR register.

Receiver mode: The first data byte is received automatically in the DR register

using the least significant bit of the address.

Then, the following data bytes are received one by one after reading the DR

OAR1

Reset value: 0000 0000 (00h)

543

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

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