RT3606BC datasheet(64/72 Pages) RICHTEK

64 / 72 page

RT3606BC

www.richtek.com

DS3606BC-04 June 2016

is a registered trademark of Richtek Technology Corporation.

Ramp Compensation

G-NAVPTM topology is one type of ripple based control

that has fast transient response and can lower BOM cost.

However, ripple based control usually has poor noise

immunity. The RT3606BC provides the ramp compensation

in AXG VR to increase noise immunity and reduce jitter at

the switching node. Figure 33 shows the ramp

compensation.

Noise Margin

VCOMPA

Noise Margin

IMONA-VREF

w/o ramp compensation

w/ ramp compensation

IMONA-VREF

VCOMPA

Figure 33. Ramp Compensation

For the RT3606BC, the ramp compensation also needs

to be considered during mode transition from PS0/1 to

PS2. For achieving smooth mode transition into PS2, a

proper ramp compensation design is necessary. Since

the ramp compensation needs to be proportional to the

on-time, then RAMP is set as

Quick Response (QR) Mechanism

As presented in QR mechanism section of CORE VR,

RT3606BC also supports QR function in AXG VR. The

output voltage signal behavior needs to be detected so

that QR mechanism can be trigged. The output voltage

signal is via a remote sense line to connect at VSENA

pin that is shown in Figure 34. The QR mechanism needs

to set QR width and QR threshold. Both definitions are

shown in Figure 22. A proper QR mechanism set can meet

different applications. SETA2 can set QR threshold and

QR width by internal current source 80

μA with multi-

function pin setting mechanism.

Figure 34. Simplified QR Trigger Schematic

For example, QR threshold 20mV/10mV at PS0/PS1 and

2.22 x TON QR width are set. According to the Table 12,

the set voltage should be between 0.4504V and 0.4723V.

Please note that a high accuracy resistor is needed for

this setting accuracy, < 1% error tolerance is

recommended. In the Table 12, there are some

“NA”marks in QRWIDTH section. It means that user

should not use it to avoid the possibility of shift digital

code due to tolerance concern.

133%

400k



VSENA

QR Pulse

Generation

Circuit

CMP

QR_width

QR_TH

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