RT3606BC datasheet(67/72 Pages) RICHTEK

67 / 72 page

RT3606BC

DS3606BC-04 June 2016

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is a registered trademark of Richtek Technology Corporation.

Current Monitor, IMONA

RT3606BC includes a current monitor (IMONA) function

which can be used to detect over current protection and

the maximum processor current ICCMAXA, and also sets

a part of current gain in the load-line setting. It produces

an analog voltage proportional to output current between

the IMONA and VREF pins.

The calculation for IMONA-VREF voltage is shown as

below :

IMONA

REF

EQA

LA1

LA2

CSA

DCR

)







Where ILA1 + ILA2 are output current and the definitions of

DCR, RCSA and REQA can refer to Figure 28.

Over Current Protection

RT3606BC provides the Over Current Protection (OCP)

which is set by the SETA1 pin in AXG VR. The OCP

threshold setting can refer to ICCMAXA current in the Table

9. For example, if ICCMAXA is set as 120A, user can set

voltage by using the external voltage divider on SETA1

pin as 0.759V typically. If 156A OCP (130% x ICCMAX)

threshold and DVID_TH (SR = 11.25mV/

μs) = 39.67mV /

DVID_TH (SR = 33.75mV/

μs) = 119mV will be set.

According to Table 10, the set voltage should be between

0.4755V and 0.4974V. When output current is higher than

the OCP threshold, OCP is latched with a 40

μs delay to

prevent false trigger. Besides, the OCP function is masked

when dynamic VID transient occurs, and soft-start period.

And the OCP function will re-active after 46

μs of DVID or

soft-start alert is asserted.

Output Over-Voltage Protection

An OVP condition is detected when the VSENA pin is

150mV more than VID. as VID > 1V. If VID < 1V, the OVP

is detected when the VSEN pin is 350mV more than 1V.

When OVP is detected, the high-side gate voltage

UGATEAx is pulled low and the low-side gate voltage

LGATEAx is pulled high, OVP is latched with a 0.5

μs

delay to prevent false trigger. Besides, the OVP function

will be masked during DVID and soft-start period. After

μs of DVID or soft-start alert is asserted, the OVP

function will re-active.

Negative Voltage Protection

Since the OVP latch continuously turns on all low-side

MOSFETs of the VR, the VR will suffer negative output

voltage. When the VSENA detects a voltage below

−0.07V

after triggering OVP, the VR triggers NVP to turn off all

low-side MOSFETs of the VR while the high-side

MOSFETs remain off. After triggering NVP, if the output

voltage rises above 0V, the OVP latch restarts to turn on

all low-side MOSFETs. Therefore, the output voltage may

bounce between 0V and

−0.07V due to OVP latch and

NVP triggering. The NVP function will be active only after

OVP is triggered.

Current Loop Design in Details

Figure 35 shows the whole current loop structure. The

current loop plays an important role in the RT3606BC that

can decide ACLL performance, DCLL accuracy and

ICCMAXA accuracy. For ACLL performance, the correct

compensator design is assumed, if RC network time

constant matches inductor time constant LAX / DCRX, an

expected load transient waveform can be designed. If RXCX

network time constant is larger than inductor time constant

LAX / DCRX, VAXG waveform has a sluggish droop during

load transient. If RXCX network is smaller than inductor

time constant LAX /DCRX, a worst VAXG waveform will sag

to create an undershooting to fail the specification.

For DCLL performance and ICCMAXA accuracy, since the

copper wire of inductor has a positive temperature

coefficient, when temperature goes high in the heavy load

condition, DCR value goes large simultaneously. A resistor

network with NTC thermistor compensation connecting

between the IMONA to REF pins is necessary, to

compensate the positive temperature coefficient of inductor

DCR. The design flow is as presented in current loop

design in details of CORE VR.

RT3606BC 데이터시트(PDF) 67 Page - Richtek Technology Corporation

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