IMX7SCEC datasheet(64/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

Figure 29 shows the LPDDR3 read timing diagram. The timing parameters for this diagram appear in

Table 45.

Figure 29. LPDDR3 read cycle

Table 44. LPDDR3 write cycle1,2,3

1 To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQS in

the middle of DRAM_DATAxx window.

2 All measurements are in reference to V

ref level.

3 Measurements were done using balanced load and 25 Ω resistor from outputs to DDR_VREF.

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

LP17

DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P

(differential strobe)

tDS

275

—

LP18

DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P

(differential strobe)

tDH

275

—

LP21

DRAM_SDQSx_P latching rising transitions to associated clock edges

tDQSS

-0.25

+0.25

tCK

LP22

DRAM_SDQSx_P high level width

tDQSH

0.4

—

tCK

LP23

DRAM_SDQSx_P low level width

tDQSL

0.4

—

tCK

Table 45. LPDDR3 read cycle1,2,3

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P

in the middle of DRAM_DATA_xx window.

2 All measurements are in reference to V

ref level.

3 Measurements were done using balanced load and 25 Ω resistor from outputs to DDR_VREF.

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

LP26

Minimum required DRAM_DATAxx valid window width for LPDDR3

—

460

—

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